![](https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhwk7LSGpiuBhc7S7htNOcCZBgHohX0ZGb78PNt1Ibk07pGo0BsfJd-4Aqb7h9jU3IjJQZ0grcgM8REc1x886BAnIjHo3R7KSOIzrgxNyFrL7oqy7JELHnwZxbqb_hLgPPxjXm0/s320/mmc_wires.jpg)
Any-hoo, once I've done the last few wires, I'll try the code I have for reading the card and see how close I got...chances are it'll need lots of tweeking to get it working right.
GETBIT3 macro
stx port ; Clock pulse
sty port ;
cpy port ; if Databit is 0, then Carry clear, else set.
rol
endm
GETBIT macro
stx port ; Clock pulse
sty port ;
asl ; Shift incoming data to make space for new bit
bit port
bmi !skip ; Bmi is reversed
ora #1
!skip
endm
CLOCK PORT
+--+--+
GND | 1| 2| VCC (+5V)
+--+--+
/INT | 3| 4| /SPARE_CS
+--+--+
/RTC_CS | 5| 6| /PWR_BAD
+--+--+
/IORD | 7| 8| /IOWR
+--+--+
A3 | 9|10| A2
+--+--+
A1 |11|12| A0
+--+--+
D7 |13|14| D6
+--+--+
D5 |15|16| D4
+--+--+
D3 |17|18| D2
+--+--+
D1 |19|20| D0
+--+--+
GND |21|22| /RESET
+--+--+
Connection to C64 Expansion Port
---------------------------------
Clock Port Signal | Expansion Port Signal
-----------------------------------------------------
GND <=> GND (22 and Z, not 1 and A)
VCC <=> +5V (2 and 3)
/INT <=> /NMI
A0-A3 <=> A0-A3
D0-D7 <=> D0-D7
/RESET <=> /RESET
sei
lda #$ff
sta $fdda ; Enable Upper and Lower external banks
/WRITE = A15* /A14* PH2* /RW ; WRITE Enable (32-48k)
/CS = /C1LOW* A15* /A14* PH2* RW ; Chip Select on READ access (32-48k)
+ A15* /A14* PH2* /RW ; On WRITE access (32-48k)
/OE = /C1LOW* A15* /A14* PH2* RW ; Output ENable on READ access (32-48k)
WR = A15* A14* A13* A12* A11* A10* A9* /A8* PH2* /RW.... and I've done all the work of those 4 other chips! Great stuff. Now I can actually try out the external 256k RAM pack idea I had, where I dont modify anything internally... could be neat if it works!
ldx #39
ScrollLoop
lda BackBuffer,x
sta HWScreen2+$400+(40*00),x
lda BackBuffer,x
sta HWScreen2+$400+(40*01),x
lda BackBuffer,x
sta HWScreen2+$400+(40*02),x
lda BackBuffer,x
sta HWScreen2+$400+(40*03),x
lda BackBuffer,x
sta HWScreen2+$400+(40*04),x
lda BackBuffer,x
sta HWScreen2+$400+(40*05),x
lda BackBuffer,x
sta HWScreen2+$400+(40*06),x
lda BackBuffer,x
sta HWScreen2+$400+(40*07),x
lda BackBuffer,x
sta HWScreen2+$400+(40*08),x
lda BackBuffer,x
sta HWScreen2+$400+(40*09),x
lda BackBuffer,x
sta HWScreen2+$400+(40*10),x
lda BackBuffer,x
sta HWScreen2+$400+(40*11),x
lda BackBuffer,x
sta HWScreen2+$400+(40*12),x
lda BackBuffer,x
sta HWScreen2+$400+(40*13),x
lda BackBuffer,x
sta HWScreen2+$400+(40*14),x
lda BackBuffer,x
sta HWScreen2+$400+(40*15),x
lda BackBuffer,x
sta HWScreen2+$400+(40*16),x
lda BackBuffer,x
sta HWScreen2+$400+(40*17),x
lda BackBuffer,x
sta HWScreen2+$400+(40*18),x
lda BackBuffer,x
sta HWScreen2+$400+(40*19),x
lda BackBuffer,x
sta HWScreen2+$400+(40*20),x
dex
jpl ScrollLoop1
rts
opt prg
opt C64=START ; Insert BASIC header, and jump to start of the code
opt A65816 ; Set 65816 assembler mode
org $1000
START:
longa off
longi off
sei
clc ; Set processor to 65816
xce ; Set 16bit processor mode
rep #$30
longi on
longa on
lda #$0000
sta $20
Here:
lda $20
ldx #$1000
Here2:
sta $0400,x
dex
bne Here2
inc $20
jmp Here
EOR (dp,X)
EOR sr,S
EOR dp
EOR [dp]
EOR #const
EOR addr
EOR >long
EOR (dp),Y
EOR (dp)
EOR (sr,S),Y
EOR dp,X
EOR [dp],Y
EOR addr,Y
EOR addr,X
EOR >long,X
LongA off
LongI off
lda #$ff
adc #$55
and #$fe
cmp #$12
eor #$55
ora #$55
sbc #$55
bit #$55
ldx #$23
cpx #$55
ldy #$23
cpy #$55
LongA on
LongI on
lda #$ffff
adc #$5125
and #$fe34
cmp #$1112
eor #$5544
ora #$5555
sbc #$5566
bit #$5532
ldx #$2312
cpx #$5542
ldy #$2363
cpy #$5513
inc a
opcode [$00]
opcode [$00],y